Method and apparatus for locking self-timed pulsed clock
US6573772B1 · kind B1 · utility
1Cited by
11References
9Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 30, 2000 |
| Grant date | Jun 3, 2003 |
| Priority date | — |
| Expiry date | Oct 7, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356139
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for generating multiple locked self-timed pulsed clock signals is disclosed. Race margins are reduced over separate clock generating circuits by sharing the necessary delay circuit elements between the multiple clock generating circuits. An edge is gated with a delayed edge to form the first clock pulse. A subsequent second clock pulse is generated by gating a partially-delayed edge with the first clock pulse, which minimizes race margins and pulse evaporation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.