High speed analog to digital converter
US6573853B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | May 31, 2002 |
| Grant date | Jun 3, 2003 |
| Priority date | — |
| Expiry date | May 31, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/365
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An analog to digital converter includes a reference ladder, a track-and-hold amplifier tracking an input signal with its output signal during the phase &psgr;1 and holding a sampled value during, a coarse analog to digital converter having a plurality of coarse amplifiers each inputting a corresponding tap from the reference ladder and the output signal, a fine analog-to-digital converter having a plurality of fine amplifiers inputting corresponding taps from the reference ladder and the output signal, the taps selected based on outputs of the coarse amplifiers, a clock having phases &psgr;1 and &psgr;2, a circuit responsive to the clock that receives the output signal, the circuit substantially passing the output signal and the corresponding taps to the fine amplifiers during the phase &psgr;2 and substantially rejecting the output signal and the corresponding taps during the phase &psgr;1, and an encoder converting outputs of the coarse and fine amplifiers to an N-bit digital signal representing the input signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.