Sample rate converters for video signals
US6573940B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 27, 2000 |
| Grant date | Jun 3, 2003 |
| Priority date | — |
| Expiry date | Mar 27, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N9/646
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A sample rate converter that includes a number of selector elements coupled to a summing circuit. Each selector element receives a respective set of one or more processed data samples and provides one of the processed data samples. Each processed data sample is generated by delaying an input sample by zero or more clock cycles and scaling the sample by a particular scaling factor (e.g. 2N, where N is 0, 1, 2, and so on). The summing circuit receives and combines the processed data samples from the selector elements to generate an output sample. A delay and scaler circuit can receive the input sample and provide one set of processed data samples for each selector element. The delay and scaler circuit can include one or more delay elements coupled in series and to a scaling circuitry that scales selected ones of the input and delayed samples. The scaling can be implemented by simply bit-shifting the samples. The elements of the sample rate converter can be configured to implement a K-tap, P-phase interpolator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.