Dynamic random access memory with low power consumption
US6574150B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 21, 2002 |
| Grant date | Jun 3, 2003 |
| Priority date | — |
| Expiry date | Jun 21, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/147
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A low power consumption type dynamic random access memory (DRAM) operable with reduced current consumption responsive to an external signal, without causing occurrence of malfunction during low current consumption. An input circuit for receiving signals, a memory array for holding data, and a peripheral circuit for controlling the memory array are driven by an internal voltage supplied by two groups of internal voltage receiving circuits, while an output circuit for outputting signals is driven by an external power supply. The two groups of internal voltage receiving circuits are deactivated in response to an externally provided power supply control signal, and the output circuit is controlled so as to be in a high impedance condition with voltage of the external power supply being applied thereto.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.