Mechanism to minimize failure in differential sense amplifiers
US6574160B1 · kind B1 · utility
9Cited by
4References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 11, 2002 |
| Grant date | Jun 3, 2003 |
| Priority date | — |
| Expiry date | Feb 11, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/065
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, a memory is disclosed. The memory includes a differential sense amplifier that receives a data input and a complementary data input; and a switching mechanism, coupled to the amplifier, that switches the data input and the complementary data input to minimize a negative bias temperature instability (NBTI) effect on the amplifier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.