Data flow enhancement for processor architectures with cache
US6574682B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 23, 1999 |
| Grant date | Jun 3, 2003 |
| Priority date | — |
| Expiry date | Nov 23, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0848
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides for data flow enhancement in processor architectures having one or more caches by allowing DMA-type transfers to and from these caches. Specific examples allow such direct transfers between a peripheral logic device and the cache memory, or between either the main memory or a special memory and the cache memory. This is done by the processor reserving a portion of cache for the direct transfer, which is then carried out by a DMA-type controller. While this transfer is occurring, the processor is able to carry out other tasks and access the unreserved portion of cache in the normal manner. In the preferred embodiment, the transfer is performed by a cycle stealing technique. Once the transfer is complete, the reserved portion of the cache may be accessed by the processor. The size of the reservable portion may either be fixed or dynamically determined by the operating system based on factors such as task flow management and data transfer rates. In a preferred embodiment, the operating system works in concert with the cache organized into cache lines, assigning each cache line an address tag field, with particular values of the address tag indicating tha…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.