Microprocessor with non-aligned scaled and unscaled addressing
US6574724B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2000 |
| Grant date | Jun 3, 2003 |
| Priority date | — |
| Expiry date | Oct 5, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3555
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system having a central processing (CPU) unit and a method of operation is provided. The CPU has an instruction set architecture that is optimized for intensive numeric algorithm processing. The CPU has dual load/store units connected to dual memory target ports of a memory controller. The CPU can execute two aligned data transfers each having a length of one byte, two bytes, four bytes, or eight bytes in parallel by executing two load/store instructions. The CPU can also execute a single non-aligned data transfer having a length of four bytes or eight bytes by executing a non-aligned load/store instruction that utilizes both memory target ports. A data transfer address for each load/store instruction is formed by fetching the instruction, decoding the instruction to determine instruction type, transfer data size, and scaling selection, selectively scaling an offset provided by the instruction and combining the selectively scaled offset with a base address value. The resultant address is then provided to the memory system to initiate a data transfer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.