Dynamic power saving by monitoring CPU utilization
US6574739B1 · kind B1 · utility
165Cited by
8References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 14, 2000 |
| Grant date | Jun 3, 2003 |
| Priority date | — |
| Expiry date | Apr 14, 2020 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A CPU activity monitoring circuit is electrically connected to a CPU. This circuit monitors the state of a bus signal line on the CPU, as there is a strong correlation between the state of this line and the processing load of the CPU. This circuit can interrupt the processor to force an interrupt service call to a BIOS routine. This BIOS routine will adjust the internal clock frequency, or internal operating voltage, of the CPU based upon the perceived processing load of the CPU.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.