System and method for improving multi-bit error protection in computer memory systems
US6574746B1 · kind B1 · utility
12Cited by
16References
22Claims
0Family size
Assignee
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Key dates
| Filing date | Jul 2, 1999 |
| Grant date | Jun 3, 2003 |
| Priority date | — |
| Expiry date | Jul 2, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/102
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for storing error correction check words in computer memory modules. Check bits stored in physically adjacent locations within a dynamic random access memory (DRAM) chip are assigned to different check words. By assigning check bits to check words in this manner, multi-bit soft errors resulting from errors in two or more check bits stored in physically adjacent memory locations will appear as single-bit errors to an error correction subsystem. Similarly, the likelihood of multi-bit errors occurring in the same check word may be reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.