Testing a bus coupled between two electronic devices
US6574758B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 10, 2000 |
| Grant date | Jun 3, 2003 |
| Priority date | — |
| Expiry date | Mar 10, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/263
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bus coupled between two circuits (which may be, for example, each implemented as a single chip) is tested by transmitting from a first circuit a predetermined signal on the bus, and recognizing in the second circuit receipt of the predetermined signal. The predetermined signal indicates the beginning of a sequence of test signals that are transmitted therebetween. When any test signal in the sequence is not received correctly, an error signal is generated to specifically identify the test signal that failed, thereby to identify a faulty line in the bus. In one implementation, test signals in the sequence differ each from the other in just the location of a predetermined pattern of bits. For example, a bit pattern 1010 may be located in the beginning, middle or end of three signals of such a sequence. Therefore, in one embodiment, logic in each circuit simply shifts the bits of the predetermined pattern through different positions to obtain the first and second test signals, and such a sequence is called a “walking pattern.”
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.