Decoupled capacitance calculator for orthogonal wiring patterns
US6574782B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 15, 2000 |
| Grant date | Jun 3, 2003 |
| Priority date | — |
| Expiry date | Jun 14, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A structure and method for extracting parasitic capacitance from a multi-layer wiring structure that creates, for each wiring layer in a wiring structure, a wiring density map and measures a plurality of metal segments in a wiring layer to determine an area occupied by the metal segments. The invention calculates an up area capacitance component for each of the metal segments by multiplying the area occupied by the metal segments by a wiring density from the wiring density map of an overlying wiring layer over the metal segments and by a capacitance coefficient of the overlying wiring layer. To calculate the down area capacitance component for each of the metal segments, the invention multiplies the area occupied by the metal segments by a wiring density, from the wiring density map of an underlying wiring layer under the metal segments and by a capacitance coefficient of the underlying wiring layer. The invention combines the up area capacitance component and the down area capacitance component to form a vertical coupling capacitance component for each of the metal segments.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.