Selectively removable filler layer for BiCMOS process

US6576507B1 · kind B1 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Kenneth Bandy · Red Hook, US
• Stuart D. Cheney · South Burlington, US
• Gary L. Milo · Colchester, US
• Yutong Wu · Longbeilingcun, CN

Key dates

• Filing date: Nov 14, 2000
• Grant date: Jun 10, 2003
• Expiry date: Dec 14, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0109

Abstract

The present invention is intended for use on BiCMOS technology where the BJTs are formed after the FETs. A thin FET protection layer 26 is deposited on the raised and recessed regions 28 of the semiconductor substrate 10. A selectively removable filler layer 30 is then deposited on the FET protection layer 26 with a thickness to over-fill the recessed regions 28 of the gates 24 of the FETs. The selectively removable filler layer 30 is then planarized until the FET protection layer 26 on top of the gates 24 is exposed. The recessed regions 28 between the gates 24 are left substantially filled with selectively removable filler layer 30. The selectively removable filler layer 30 in the region where the BJT is formed is patterned and an opening 32 is made to allow for the depositing of layers of different materials 34, 36, 38, 40, 42, 44 used in the construction of the BJT. The layer of different materials 34, 36, 38, 40, 42, 44 are processed by methods known in the art to form polysilicon emitter 46 of the BJT. Due to selectively removable filler layer 30 creating a substantially planar surface in the recessed regions 28 of the FETs, little to none of the layers of different materials…