Low cost bias technique for dual plate integrated capacitors

US6576977B1 · kind B1 · utility

Assignee

• NATIONAL SEMICONDUCTOR CORPORATION · US

Inventors

• Donald St. John Beeman · Carson City, US
• Paul M. Werking · Atlanta, US

Key dates

• Filing date: Sep 17, 2002
• Grant date: Jun 10, 2003
• Expiry date: Sep 17, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/813

Abstract

An integrated dual-plate capacitor structure incorporates a small MOS transistor to reduce die area. The capacitor structure includes a semiconductor substrate having a first conductivity type and having a well region having a second conductivity type opposite the first conductivity type formed therein. An upper conductive plate and a lower conductive plate separated by a first layer of dielectric material are formed over the well region. The lower capacitor plate is separated from the upper surface of the well region by a second layer of dielectric material. A MOS transistor is formed in the semiconductor substrate. The MOS transistor includes space-apart source and drain regions of the second conductivity type that define a substrate channel region therebetween. A conductive gate is formed above the channel region and is separated therefrom by a layer of intervening dielectric material. The source region and the gate of the MOS transistor are connected to receive a bias voltage. The drain region of the MOS transistor is electrically connected to the well region. In an alternative embodiment, the drain of the MOS transistor is incorporated into the well region of the capacitor str…