Offset correction circuit
US6577183B1 · kind B1 · utility
3Cited by
10References
43Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 15, 2001 |
| Grant date | Jun 10, 2003 |
| Priority date | — |
| Expiry date | Jun 15, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45702
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An offset correction circuit loop with summing nodes, a variable gain transconductance amplifier and capacitor. The input to the loop is sent to a first summing node and then to a separate circuit. The output of the separate circuit is sent to the output of the loop and to the input of a second summing node. The second summing node subtracts the circuit output from a reference voltage and sends the result to the transconductance amplifier which outputs a corrective current which is then integrated onto the capacitor to produce a corrective input offset voltage estimate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.