Integrated circuit
US6577212B1 · kind B1 · utility
9Cited by
4References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 14, 2000 |
| Grant date | Jun 10, 2003 |
| Priority date | — |
| Expiry date | Jul 14, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H11/08
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The invention relates to an integrated gyrator structure, in which each transistor in the gyrator core (preferably MOS devices) has series feedback associated therewith. This allows for compensation over a large bandwidth of the effects of channel delay in the MOS transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.