Format programmable hardware packetizer
US6577640B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 1, 2001 |
| Grant date | Jun 10, 2003 |
| Priority date | — |
| Expiry date | Jan 23, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N21/236
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A format programmable hardware packetizer (110) receives real-time raw input data (125) from a multimedia data source (103) via an analog to digital converter (105) and a data encoder (120) gated by encoder interrupts (127). The real-time raw input data is buffered in an internal byte collector of the packetizer (110). A main CPU interrupt (117) is issued to the main processor (130) when a packet boundary code is received. The packetizer (110) formats the data according to a desired format selected on line (115) for dump to the main memory (140) while providing a managed, much lower level of interrupts to the main processor (130) on the CPU interrupt line (117). A plurality of hardware packetizers (110) can be deployed according to alternative constructions for efficient real time packetizing in various selected formats.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.