Programmable digital signal processor for demodulating digital television signals
US6577685B1 · kind B1 · utility
58Cited by
6References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 2, 1999 |
| Grant date | Jun 10, 2003 |
| Priority date | — |
| Expiry date | Aug 2, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N21/426
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A phase-lock loop circuit in a demodulator includes a timing recovery block and a carrier recovery block. The demodulator for demodulates a digital signal including symbols. The phase-lock loop includes an integrator processing a block of N samples to produce an average of the N symbols, and means for supplying the average of the N symbols to the timing recovery block and the carrier recovery block every NT period, where T is a sample time interval.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.