Binary self-correcting phase detector for clock and data recovery
US6577694B1 · kind B1 · utility
16Cited by
13References
22Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 8, 1999 |
| Grant date | Jun 10, 2003 |
| Priority date | — |
| Expiry date | Nov 8, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03D13/003
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase detector for a clock and data recovery circuit from random non-return-to zero (NRZ) data signal includes a plurality (e.g., preferably three) edge-triggered flip-flops. The incoming NRZ data are sampled by a pair of edge-triggered flip-flops using the transition of the clock generated by the clock recovery circuit. A third edge-triggered flip-flop processes the outputs from the edge-triggered flip-flop pair to indicate whether the generated clock leads or lags the received data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.