RAM with configurable depth and width
US6578104B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 1999 |
| Grant date | Jun 10, 2003 |
| Priority date | — |
| Expiry date | Jun 30, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A RAM device, such as the type embedded in a programmable logic device, is configurable to alter the depth of the addressable elements and the width of the number of data bits received or produced by the RAM device. The RAM device includes a number of address ports for receiving the read and/or write address signals, but the RAM device may be configured such that the depth requires fewer address signals then there are address ports. Likewise, the RAM device includes a number of input and output data ports for receiving and producing the data bits, but the width of the RAM device may be configured such that the number of data bits actually received or produced are less than the number of data ports. The depth and the width of the RAM device are configured together so that the depth is increased when the width is decreased and vice versa. This permits a number of appropriately configured RAM devices to be combined to produce a deep and wide RAM circuit without requiring the use of additional logic blocks, such as buffers, inverters, and multiplexors that reduce the speed of the circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.