High performance thin film transistor and active matrix process for flat panel displays
US6580127B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 1999 |
| Grant date | Jun 17, 2003 |
| Priority date | — |
| Expiry date | Sep 30, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/00
Abstract
A transistor, in accordance with the present inventions includes a gate electrode layer formed on a substrate and an insulating layer formed on the gate electrode layer. A first conductive layer forms a first portion and a second portion separated by a gap therebetween. The gap is formed at a position corresponding to a gate electrode in the gate electrode layer. A doping layer is formed on the first portion and the second portion of the first conductive layer, forming a source and a drain for the transistor. A semiconductor layer is formed over the doping layer of the first portion and the second portion and in the gap in contact with the insulating layer such that upon activation of the gate electrode current flows across the gap directly between the first portion and the second portion in the first conductive layer. Methods for fabrication and other embodiments are also included.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.