Cell architecture to reduce customization in a semiconductor device
US6580289B2 · kind B2 · utility
274Cited by
13References
14Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 6, 2002 |
| Grant date | Jun 17, 2003 |
| Priority date | — |
| Expiry date | Jun 6, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17796
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A semiconductor device and method of testing the device having a plurality of logic cells interconnected using vias to connect routing tracks that are disposed among a plurality of layers in the device. The logic cells in the device including at least two three-input look-up tables, one two-input look-up table and a flip-flop. The components in the logic cell are connected so that any look-up table can drive at least one input of any other look-up table and where the flip-flop is connected to the look-up tables so that any look-up table can drive an input of the flip-flop.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.