High voltage output buffer using low voltage transistors
US6580291B1 · kind B1 · utility
11Cited by
39References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 18, 2000 |
| Grant date | Jun 17, 2003 |
| Priority date | — |
| Expiry date | Jun 7, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00315
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus comprising a first circuit configured to generate a first portion of an output signal in response to (i) a first supply voltage and (ii) a pullup signal and a second circuit configured to generate a second portion of said output signal in response to (i) a second supply voltage and (ii) a pulldown signal, wherein said first and second circuits are implemented with transistors that normally can only withstand said second supply voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.