Digital circuit for, and a method of, synthesizing an input signal
US6580299B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 5, 2002 |
| Grant date | Jun 17, 2003 |
| Priority date | — |
| Expiry date | Apr 5, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/16
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and a digital circuit for synthesizing an input signal to produce an output signal are provided. The circuit includes a delay unit with a delay input and a delay output, a switch, and a controller. The selectively switch routes the input signal to the delay input whereafter the switch routes the delay output to the delay input. The controller controls the delay unit in response to the input signal and the output signal. A counter is provided to count a predetermined number of times the delay output is routed to the delay input whereafter the input signal is routed to the delay input to trigger the delay input. The digital circuit synthesizes the input signal to define a Delay-Locked loop (DLL) in which the delay unit is a voltage controlled delay line (VCDL). The invention extends to a computer program product executing the method and to an embedded circuit including the digital circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.