Generating a clock signal
US6580305B1 · kind B1 · utility
19Cited by
5References
45Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 29, 1999 |
| Grant date | Jun 17, 2003 |
| Priority date | — |
| Expiry date | Dec 29, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus which generates a clock signal includes a first phase mixer which generates an initial clock signal based on a first set of reference clocks and a buffer which adds a first predetermined delay to the initial clock signal to produce a first clock signal. A phase detection circuit detects a difference in phase between the first clock signal and a master clock signal, and a control circuit selects a second set of reference clocks based on the difference in phase and a second predetermined delay. A second phase mixer generates an output clock signal based on the second set of reference clocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.