Interface circuit for a differential signal
US6580323B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 19, 2002 |
| Grant date | Jun 17, 2003 |
| Priority date | — |
| Expiry date | Feb 19, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45352
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit comprises a first (6) and a second (21) input for receiving a differential signal and a buffer circuit. The buffer circuit comprises an input stage with a first (2, 2a, 2b, 13, 13a, 13b) and a second (8, 18) differential amplifier, a current source for supplying a first current of a first polarity to the first differential amplifier (2, 2a, 2b, 13, 13a, 13b), and a second current source for supplying a second current of opposite polarity to the second differential amplifier (8, 18). Each of the differential amplifiers (2, 13; 8, 18) has a first input (5,7) coupled to the first input (6) of the circuit and a second input (14, 19) coupled to the second input (21) of the circuit. Said circuit further comprises a combination stage comprising at least one chain with a first node (58) coupled to an output (58) of the first differential amplifier (2, 2a, 2b, 13, 13a, 13b) and a second node (84) coupled to an output (84) of the second differential amplifier (8, 18), and an active circuit, a main current path of which is coupled between the first (58) and the second (84) node. The control electrode of the active circuit is coupled to a bias voltage. The active circuit comprises a …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.