Selectable input buffer control system
US6580359B1 · kind B1 · utility
9Cited by
10References
13Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 28, 1999 |
| Grant date | Jun 17, 2003 |
| Priority date | — |
| Expiry date | Oct 28, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/002
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A selectable input buffer control system includes at least one input buffer; a plurality of input receivers associated with each input buffer; an addresser circuit for addressing each input receiver; and a selection circuit associated with each input buffer for enabling its associated input buffer in response to the addressing of any one or more of the input receivers associated with that input buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.