High resolution ADC based on an oversampled subranging ADC
US6580383B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 1, 2000 |
| Grant date | Jun 17, 2003 |
| Priority date | — |
| Expiry date | Nov 1, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/20
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A high performance ADC apparatus. The inventive apparatus comprises a front end ADC baseline device providing a baseline bit size at a baseline data rate and a selected dynamic range at a baseline clock rate. A first circuit is enabled for translating upward, by a selected factor, a reference clock to produce the baseline clock rate. A second circuit is enabled for decimating the baseline data rate of the baseline device to a data rate reduced by the selected factor, so as to achieve an oversampling rate equal to the selected factor. A final circuit is employed for producing an output data rate less than the baseline clock rate by the selected factor with the final resolution. The method for producing this result includes providing the baseline device having a selected dynamic range at a baseline clock rate; generating the baseline clock rate by translating a reference clock upward by a selected factor; decimating the data rate of the baseline device to a slower data rate so as to achieve a selected degree of oversampling; and producing an output data rate as a sub-multiple of the baseline clock rate with the selected output resolution at the slower data rate. The architecture incl…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.