Flash memory device capable of checking memory cells for failure characteristics
US6580644B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 4, 2002 |
| Grant date | Jun 17, 2003 |
| Priority date | — |
| Expiry date | Mar 4, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A nonvolatile semiconductor memory device is provided, which supports an erase verify operation mode to determine whether an erased memory cell is lower than a maximal threshold voltage (e.g., 3V), and a test verify operation mode to determine whether the erased memory cell has a progressive fail characteristic. Once the memory device enters the test verify operation mode, a wordline voltage to be applied to a memory cell and a reference wordline voltage to be applied to a reference cell are generated. The wordline and reference wordline voltages generated in the test verify operation mode are set to be higher than those generated in the erase verify operation mode. This makes it possible to compare current flowing through the memory cell and reference cell at more than one level and to check a memory cell for a progressive (or potential) failing characteristic.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.