Priority encoder circuit and method for content addressable memory
US6580652B2 · kind B2 · utility
Inventors
Key dates
| Filing date | Nov 12, 2002 |
| Grant date | Jun 17, 2003 |
| Priority date | — |
| Expiry date | Nov 12, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit selects a highest priority signal from a plurality of input signals. The circuit comprises the following components. A plurality of serially coupled input blocks, each of which are coupled to a corresponding one of a plurality of input lines for receiving respective ones of the input signals and providing corresponding output signals. A pre-charging device coupled between a first supply voltage terminal and a first one of the serially coupled input blocks. The pre-charging device couples the supply voltage to the first one of the serially coupled input blocks in response to a clock pulse signal transition. An activation device coupled between a second supply voltage terminal and a last one of the serially coupled input blocks. The activation device couples the second supply voltage to the last one of the serially coupled input blocks in response to an activation signal transition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.