Computer-system-on-a-chip with test-mode addressing of normally off-bus input/output ports
US6581019B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 20, 2000 |
| Grant date | Jun 17, 2003 |
| Priority date | — |
| Expiry date | Mar 20, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/27
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An embedded-controller-based system, such as a personal digital assistant (PDA), includes a system-on-a-chip with a processor, system bus, memory, and system-bus peripherals. The system-bus peripherals include connections to data paths that are not accessible from the system bus during execution of application programs. Associated with these connections are test drivers that include registers that can be written to by the processor via the system bus for software controllability. When the processor executes a test program, it writes test values to these registers. Some bits of the test values are used to control multiplexers so that they can decouple function block ports from the non-system-bus connections and then couple the remaining bits of the registers. In this way, a test program can write data directly to the non-system bus connections. The results of the test data being applied at the source of inter-block connections can be read from the destinations using test samplers. The test samplers can be taps to function block ports that are multiplexed to the system bus for reading during a test procedure for software observability. Thus, both bus connections and non-bus connectio…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.