Interrupt controller and a microcomputer incorporating this controller
US6581119B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 21, 2000 |
| Grant date | Jun 17, 2003 |
| Priority date | — |
| Expiry date | Aug 23, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
To downsize the circuit scale of a CPU in a microcomputer capable of executing multiple interrupt, an interrupt controller includes an interrupt mask level register. The CPU temporarily transfers or stacks processing data into a RAM. The processing data include a PSR (i.e., system register) value and a PC (i.e., program counter) value of the interrupt processing presently running in CPU. At the same time, the CPU sends a stack signal “STK” to the interrupt controller. In response to the stack signal “STK”, the interrupt controller temporarily transfers the interrupt mask level stored in the register into the RAM. When the CPU restarts the suspended interrupt processing, the CPU reads the PSR value and the PC value from the RAM while the CPU produces a return signal “RTN.” In response to the return signal “RTN”, the interrupt mask level is returned from the RAM to the register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.