Multiple source generic memory access interface providing significant design flexibility among devices requiring access to memory
US6581145B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 3, 1999 |
| Grant date | Jun 17, 2003 |
| Priority date | — |
| Expiry date | Mar 3, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1605
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electronic system is described herein, the apparatus including at least two devices requiring access to memory, a memory controller, and a memory, the memory being coupled to an output of the memory controller. The memory controller includes at least one input and at least one output; one memory controller input being operatively coupled to at least one of the devices through a shared bus, and one memory controller output being operatively coupled to at least one device through a shared bus. The shared bus includes a plurality of device select lines, a plurality of address lines, a plurality of write data lines, a plurality of read data lines, a plurality of read select lines, and at least two device_request lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.