Methods and apparatus for instruction addressing in indirect VLIW processors
US6581152B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 11, 2002 |
| Grant date | Jun 17, 2003 |
| Priority date | — |
| Expiry date | Feb 11, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3853
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An indirect VLIW (iVLIW) architecture is described which contains a minimum of two instruction memories. The first instruction memory (SIM) contains short-instruction-words (SIWs) of a fixed length. The second instruction memory (VIM), contains very-long-instruction-words (VLIWs) which allow execution of multiple instructions in parallel. Each SIW may be fetched and executed as an independent instruction by one of the available execution units. A special class of SIW is used to reference the VIM indirectly to either execute or load a specified VLIW instruction (called an “XV” instruction for “eXecute VLIW”, or LV for “Load VLIW”). In these cases, the SIW instruction specifies how the location of the VLIW is to be accessed. Other aspects of this approach relate to the application of data memory addressing techniques for execution or loading of VLIWs that parallel the addressing modes used for data memory accesses. These addressing techniques provide tremendous flexibility for VLIW instruction execution.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.