Dominant error correction circuitry for a Viterbi detector
US6581181B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 29, 2000 |
| Grant date | Jun 17, 2003 |
| Priority date | — |
| Expiry date | Mar 29, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11B20/10009
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The apparatus corrects a data detection error caused by baseline wandering in an optical PRML read channel. The apparatus includes error detection circuitry and error correction circuitry. The error detection circuitry monitors a serial output signal from the optical PRML read channel and a first set of input signals to the optical PRML read channel to detect an error event associated with baseline wandering. The error detection circuitry deems the error event to have occurred when three conditions are satisfied. First, a bit sequence represented by the serial output signal matches a first bit sequence associated with the error event. Second, a first difference in a first set of consecutive values represented by the first set of input signals is within a first range of values associated with the error event. Third, a second difference in a second set of consecutive values of the first input signal is within a second range of values associated with the error event. The error detection circuitry responds to satisfaction of all three conditions by asserting an error signal. The error correction circuitry responds to assertion of the error signal by modifying a pair of consecutive bits…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.