Method of collectively packaging electronic components
US6581279B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 4, 2001 |
| Grant date | Jun 24, 2003 |
| Priority date | — |
| Expiry date | Apr 4, 2021 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49144
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Method of collectively packaging a plurality of electronic components formed in a first substrate, wherein the electronic components are separated from one other by separation strips associated with a plurality of conducting tracks formed on a second substrate. The conducting tracks on the second substrate are associated with contact pads of the components in the first substrate. Each conducting track on the second substrate includes a connection strip arranged to coincide with associated depressions in the first substrate when the first and second substrates are mated. After mating, the components are separated into individualized electronic modules by forming proximal trenches in the first substrate and distal trenches in the second substrate. The proximal trenches are formed around the components in the first substrate to open up into the depressions in the first substrate. The distal trenches are formed further away from the components than the proximal trenches in regions comprising the connection strips on the second substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.