Structure and method for fabrication of a leadless chip carrier with embedded antenna
US6582979B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 26, 2001 |
| Grant date | Jun 24, 2003 |
| Priority date | — |
| Expiry date | Jul 26, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A substrate has a top surface for receiving a semiconductor die. An antenna is patterned on the bottom surface of the substrate. The antenna is accessible by coupling it to a via and, through the via, to a substrate signal bond pad and a semiconductor die signal bond pad. In one embodiment, there is at least one via in the substrate. The at least one via provides an electrical connection between a signal bond pad of the semiconductor die and the printed circuit board. The at least one via provides an electrical connection between a substrate bond pad and the printed circuit board. The at least one via also provides an electrical connection between the signal bond pad of the semiconductor die and a land that is electrically connected to the printed circuit board.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.