Method for producing an integrated circuit processed on both sides
US6583030B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 15, 2001 |
| Grant date | Jun 24, 2003 |
| Priority date | — |
| Expiry date | Aug 15, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for producing an integrated circuit wherein a substrate is provided that includes a circuit structure and a first metalization structure disposed thereover comprising at least one layer with plated holes extending therethrough and into the circuit structure. The plated holes are insulated and a planarizing layer is disposed over the metalization structure. A handling wafer is applied over the substrate permitting the substrate to be thinned such that metalized connections disposed in the plated holes are exposed. A second metalization structure is provided and connected to the circuit structure and/or the first metalization structure by the metalized connections.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.