Single-edge clock adjustment circuits for PLL-compatible, dynamic duty-cycle correction circuits
US6583657B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 20, 2002 |
| Grant date | Jun 24, 2003 |
| Priority date | — |
| Expiry date | Jun 20, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1565
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A duty cycle correction circuit is configured to adjust the duty cycle of a clock signal in a clock distribution network. The duty cycle correction circuit adjusts the duty cycle of the clock signal by adjusting the transitional delay in a single edge of each clock pulse of the clock signal without interrupting the other edge of each clock pulse of the clock signal. This feature enables the duty cycle correction circuit to adjust the duty cycle of the clock signal without interrupting the operation of a phase-locked loop (PLL) used in the clock distribution network. The duty cycle correction circuit includes a delay-control circuit coupled to a clock-inverter circuit. The delay-control circuit generates a delay-control voltage, which is provided to the clock-inverter circuit to control the transitional delay in a single edge of each clock pulse of the clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.