Variable clock rate display device
US6583785B2 · kind B2 · utility
3Cited by
3References
3Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 5, 2001 |
| Grant date | Jun 24, 2003 |
| Priority date | — |
| Expiry date | Aug 15, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G5/18
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A variable clock rate device and a method of operating the device. When the display device is first initialized, a pixel clock and a memory read clock are set to the largest values. If the CPU reads from the memory area, the frequency of the pixel clock and the memory read clock is adjusted according to the frequency of the CPU update on-screen memory and the variation of the CPU change on-screen memory block. On the contrary, if the CPU does not initiate any updating, the pixel clock and the memory read clock are tuned down to the smallest possible values to conserve electricity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.