Multi-finger current ballasting ESD protection circuit and interleaved ballasting for ESD-sensitive circuits
US6583972B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jun 14, 2001 |
| Grant date | Jun 24, 2003 |
| Priority date | — |
| Expiry date | Sep 4, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
Abstract
A multi-finger electro-static discharge (ESD) protection circuit has at least two first resistive channels defining input fingers. At least two field effect transistor (FET) channels, each having a drain and source are connected to corresponding ones of the at least two input fingers. The gate terminals of at least one of the at least two FETs are configured to be biased by an ESD potential applied to the drain electrodes to reduce the turn-on potential of the ESD device. At least two second resistive channels are connected between a corresponding one of the source terminals of the at least two FETs and a circuit return path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.