Patent · US Expired

SRAM emulator

US6584036B2 · kind B2 · utility

16Cited by

11References

32Claims

0Family size

Assignee

Atmos Ltd · CA

Inventors

Wlodek Kurjanowicz · Arnprior, CA
Jacek Misztal · Ottawa, CA

Key dates

Filing date	Mar 14, 2002
Grant date	Jun 24, 2003
Priority date	—
Expiry date	Mar 14, 2022

Classification

Technology area (CPC G)Physics
CPC primaryG11C2207/2281
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Generally, the present invention provides memory controller for providing a synchronous SRAM interface to an embedded SDRAM. To achieve maximum performance SDRAM timing, row circuitry is emulated in the controller to produce SDRAM control signals. Control signal timing is optimized for read and write operations and can be flexibly adjusted using control registers. Since the timing of DRAM control signals is based on the embedded DRAM timing emulation, all margins can be minimized and the performance of the memory can be maximized. The SRAM interface can operate in a wide range of clock frequencies, which are not restricted to ratios of multiples of the embedded DRAM clock frequency.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.