LSI Architecture and implementation of MPEG video codec
US6584156B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 17, 1998 |
| Grant date | Jun 24, 2003 |
| Priority date | — |
| Expiry date | Jul 17, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/61
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Flexible VLSI architecture implements of MPEG video processing unit (VPU) for encoding and decoding. In encoding mode, VPU performs compression operations on digitized video input per MPEG standard; and in decoding mode, VPU performs decompression operations on video bitstream per MPEG standard. VPU modules include: Discrete Cosine Transformation (DCT), Inverse Discrete Cosine Transformation (IDCT), Quantization (QNT), Inverse Quantization (IQ), Variable Length Encoding (VLC), Variable Length Decoding (VLD) and Motion Compensation (MC). VPU functions in half duplex, and hardware modules are shared between encode/decode modes. Architecture provides low-cost, flexible and efficient solution to implement real-time MPEG codec. Specific system configuration is not required, and general interface supports various operating conditions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.