Apparatus and method for address modification in a direct memory access controller
US6584514B1 · kind B1 · utility
3Cited by
5References
17Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 27, 2000 |
| Grant date | Jun 24, 2003 |
| Priority date | — |
| Expiry date | Jan 12, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a digital signal processing unit, addressing apparatus implements a multiplicity of addressing modes. The addressing modes include a circular buffer memory mode, a frame mode, and a sorting mode. To increase the speed of the address modification, the index, the index in the presence of a positive wrap-around, and the index in the presence of negative wrap-around are determined together. Other apparatus determines the addressing mode and provides control signals for the selection of the correct index. The correct index is combined with the base address to provide the next new address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.