Scaleable bandwidth interconnect for simultaneous transfer of mixed pleisiochronous digital hierarchy (PDH) clients
US6584521B1 · kind B1 · utility
13Cited by
3References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 27, 1999 |
| Grant date | Jun 24, 2003 |
| Priority date | — |
| Expiry date | Dec 27, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J2203/0026
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A scaleable bandwidth interconnect (SBI) for interconnection of physical layer devices with link layer devices which includes an ADD BUS interface operative to receive data from one of the link layer devices and direct it to one of the physical layer devices and a DROP BUS interface operative to receive data from one of the physical layer devices and direct it to one of the link layer devices. By utilizing buses to access each of the physical layer devices and the link layer devices permits interfacing between a high density of physical layer devices and a high density of link layer devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.