Information processing system, bus arbiter, and bus controlling method
US6584530B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 19, 2002 |
| Grant date | Jun 24, 2003 |
| Priority date | — |
| Expiry date | Jun 19, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/364
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a means for preventing execution of a transaction such as main storage access from obstruction by bus competition with low-speed IO access and improving the bus occupation efficiency.Apparatus for preventing execution of a transaction such as storage access from obstruction by bus competition with low-speed IO access. The invention includes a first bus, a second bus, a plurality of modules connected to both buses, a bus conversion unit for performing protocol conversion of information between both buses, a bus arbiter for arbitrating a bus occupation right request of a bus master, and a storage for storing access data up to a predetermined amount when the access destination is a predetermined module. Each bus master outputs access destination information and when the bus arbiter judges that one of the bus masters issues a bus occupation right request, the bus arbiter refers to the access destination information and the data storage status of the storage and decides whether to give a bus occupation right to the bus master.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.