Arbitration circuit with plural arbitration processors using memory bank history
US6584531B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 27, 2000 |
| Grant date | Jun 24, 2003 |
| Priority date | — |
| Expiry date | Apr 27, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1663
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for arbitrating access to a memory, which has a plurality of banks. The method includes arbitrating with a plurality of processors. Each processor is associated with one of a plurality of data ports and has a plurality of arbitration cycles, including a current cycle and a most recent cycle preceding the current cycle. Each processor receives memory access requests from all of the data ports, wherein each memory access request is associated with one of the memory banks. Each processor selectively grants the data port associated with that processor access to the memory for the current cycle based on the banks associated with the memory access requests of each data port, the data port that was granted access to the memory during the preceding cycle, and the memory bank that was accessed during the preceding cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.