Bus transaction accelerator for multi-clock systems
US6584536B1 · kind B1 · utility
10Cited by
10References
30Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 7, 1999 |
| Grant date | Jun 24, 2003 |
| Priority date | — |
| Expiry date | Oct 7, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/02
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A bus transaction accelerator, incorporating an innovative control register and status register circuit. The innovative accelerator allows systems with different clocks to handshake in the background, thereby reducing bus idle time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.