Shared cache structure for temporal and non-temporal instructions
US6584547B2 · kind B2 · utility
15Cited by
6References
15Claims
0Family size
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Key dates
| Filing date | Mar 9, 2001 |
| Grant date | Jun 24, 2003 |
| Priority date | — |
| Expiry date | Jul 19, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0862
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for providing cache memory management. The system comprises a main memory, a processor coupled to the main memory, and at least one cache memory coupled to the processor for caching of data. The at least one cache memory has at least two cache ways, each comprising a plurality of sets. Each of the plurality of sets has a bit which indicates whether one of the at least two cache ways contains non-temporal data. The processor accesses data from one of the main memory or the at least one cache memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.