Memory system using complementary delay elements to reduce rambus module timing skew
US6584576B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 12, 1999 |
| Grant date | Jun 24, 2003 |
| Priority date | — |
| Expiry date | Nov 12, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4239
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improvement in a Rambus memory system of the type used in personal computers. On a module level, each RIMM (Rambus Interface Memory Module) includes a positive and a negative module time delay element on the CTM (clock to master) clock line. On a system level, where a motherboard has a plurality of RIMMs coupled to a chipset (i.e. memory controller), a positive or negative system time delay element is placed on the CFM (clock from master line). By virtue of the module and system time delay elements, the clock timing can be adjusted from the data timing, whereby the overall TQ (timing skew between clock and data) can be advantageously reduced to allow more RIMMs to be placed on the same motherboard. What is more, the module and system delays also improve timing margins on the standard Rambus channel so as to increase the robustness of a conventional Rambus system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.