Fast method of I/O circuit placement and electrical rule checking
US6584606B1 · kind B1 · utility
22Cited by
6References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 1, 2000 |
| Grant date | Jun 24, 2003 |
| Priority date | — |
| Expiry date | Aug 29, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of analyzing I/O cell layouts for integrated circuits, such as ASICs, includes defining a proposed I/O cell layout on a selected chip image, providing a set of limit rules for electromigration, IR voltage drop and di/dt noise for the selected chip image, providing characteristics for each I/O cell type used in the proposed I/O cell layout, checking the proposed I/O cell layout by applying the limit rules to the proposed I/O cell layout and reporting all I/O cells used in the proposed I/O cell layout that do not meet the limit rules for the selected chip image.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.